A nonlinear oscillator network for gray-level image segmentation and PWM/PPM circuits for its VLSI implementation

This paper proposes a nonlinear oscillator network model for gray-level ima ge segmentation suitable for massively parallel VLSI implementation. The mo del performs image segmentation in parallel using nonlinear analog dynamics . Because of the limited calculation precision in VLSI implementation, it i s important to estimate the calculation precision required for proper opera tion. By numerical simulation, the necessary precision is estimated to be 5 bits, We propose a nonlinear oscillator network circuit using the pulse mo dulation approach suitable for an analog-digital merged circuit architectur e. The basic operations of the nonlinear oscillator circuit and the connect ion weight circuit are confirmed by SPICE circuit simulation. The circuit s imulation results also demonstrate that image segmentation can be performed within the order of 100 mu s.