A 3.3 VCMOS dual-looped PLL with a current-pumping algorithm

This paper describes a dual-looped PLL architecture to improve voltage-to-f requency linearity of VCO. The V-I converter Employing a current-pumping al gorithm is proposed to enhance the linearity of the VCO circuit. The design ed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good lin earity. The PFD circuit design technique preventing fluctuation of the char ge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 mu s at 1 GHz and the power dissipation is 92 mW.