Multithreaded architecture for multimedia processing

Citation
M. Amamiya et al., Multithreaded architecture for multimedia processing, INTEGR COMP, 7(1), 2000, pp. 19-37
Citations number
20
Categorie Soggetti
Computer Science & Engineering
Journal title
INTEGRATED COMPUTER-AIDED ENGINEERING
ISSN journal
10692509 → ACNP
Volume
7
Issue
1
Year of publication
2000
Pages
19 - 37
Database
ISI
SICI code
1069-2509(2000)7:1<19:MAFMP>2.0.ZU;2-R
Abstract
There are two fundamental problems to be solved in any scalable computer sy stem: tolerate and hide latency of remote accesses, and, tolerate and hide idling due to synchronization among parallel processes. Architectures which can not solve these issues will fail in building large-scale parallel proc essing systems. One possible solution for tolerating memory and synchroniza tion latency is the introduction of threads and fast context switching mech anism among threads. Systems which support this technique are called multit hreaded systems. Multimedia applications usually require large computing power and thus, mas sivelly parallel systems are good candidates for such tasks. Additionally, multimedia applications usually involve the processing of huge amount of da ta (e.g. audio or video information), therefore both the classical shared o r distributed memory parallel systems may be inadequate for fulfilling all the needs. Finally, multimedia applications (e.g. image processing) in some cases may require other computing model than current commodity RISC proces sors can provide. A range of multithreaded architectures can be idealistic for multimedia app lications, which is massively parallel, has distributed memory for the sake of scalability. Such architectures, which support remote memory accesses, may be a proper combination of different computing models, e.g. von Neumann n and dataflow ones. In this paper, the design space of multithreaded architectures is introduce d, and a certain architecture, called KUMP/D (Kyushu University Multimedia Processor on Datarol-II) is described. It is also shown how a multi-threade d architecture can be built in a short design cycle by using a commercial h igh-end microprocessor and easily programmable hardware devices.