A charge recycling technique for the design of low power CMOS clock drivers

The design of low power CMOS clock drivers using a charge recycling techniq ue is introduced in this paper. Considering a clock signal and its compleme nt, the half of the charge stored in the load capacitances is reused in eve ry clock edge. The proposed circuit exploits the inherent input-output dela y of the driver for the generation of all necessary control signals, using fully digital logic and conventional technology. Extensive simulations of t he circuit have been performed and the influence of various design paramete rs on its response has been studied. Compared to traditional taper buffers, power savings over 45% are obtained for the output load transitions wherea s the total power reduction decreases by 10% to 35% due to control overhead . Moreover, no speed degradation is observed but almost a duplication of th e silicon area is required.