The conventional memory organization of fast Fourier transform (FFT) proces
sors is based on Cohen's scheme, Compared Kith this scheme, our scheme redu
ces the hardware complexity of address generation by about 50% while improv
ing the memory access speed, Much power consumption in memory is saved sinc
e only half of the memory is activated during memory access, and the number
of coefficient access is reduced to a minimum by using a nem ordering of F
FT butterflies. Therefore, the new scheme is a superior solution to constru
cting high-performance FFT processors.