Pipeline reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance , it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantl y reduce both these costs. In this paper we describe the benefits of hardwa re virtualization, and show how it can be achieved using the technique of p ipeline reconfiguration. The result is PipeRench, an architecture that supp orts robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commerc ial FPGAs and DSPs in both overall performance and in performance normalize d for silicon area over a broad range of problem sizes.