Design and implementation of the MorphoSys reconfigurable computing processor

In this paper, we describe the implementation of MorphoSys, a reconfigurabl e processing system targeted at data-parallel and computation-intensive app lications. The MorphoSys architecture consists of a reconfigurable componen t (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the det ailed design implementation and the various aspects of physical layout of d ifferent sub-blocks of MorphoSys. The physical layout was constrained for 1 00 MHz operation, with low power consumption, and was implemented using 0.3 5 mu m, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typi cal data-parallel applications (video compression and automatic target reco gnition). The results indicate that the MorphoSys system can achieve signif icantly better performance for most of these applications in comparison wit h other systems and processors.