Application of reconfigurable CORDIC architectures

Reconfiguration enables the adaption of Coordinate Rotation DIgital Compute r (CORDIC) units to the specific needs of sets of applications, hence creat ing application specific CORDIC-style implementations. Reconfiguration can be implemented at a high level, taking the entire CORDIC unit as a basic ce ll (CORDIC-cells) implemented in VLSI, or at a low level such as Field-Prog rammable Gate Arrays (FPGAs). We suggest a design methodology and analyze a rea/time results for coarse (VLSI) and fine-grain (FPGA) reconfigurable COR DIC units. For FPGAs we implement CORDIC units in Verilog HDL and our objec t-oriented design environment, PAM-Blox. For CORDIC-cells, multiple reconfi gurable CORDIC modules are synthesized with state-of-the-art CAD tools. At the algorithm level we present a case study combining multiple CORDICs base d on a geometrical interpretation of a normalized ladder algorithm for adap tive filtering to reduce latency and area of a fully pipelined CORDIC imple mentation. Ultimately, the goal is to create automatic tools to map applica tions directly to reconfigurable high-level arithmetic units such as CORDIC s.