The influence of stud bumping stress on device degradation in scaled MOSFETs

Citation
N. Shimoyama et al., The influence of stud bumping stress on device degradation in scaled MOSFETs, MICROEL REL, 40(2), 2000, pp. 267-275
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONICS RELIABILITY
ISSN journal
00262714 → ACNP
Volume
40
Issue
2
Year of publication
2000
Pages
267 - 275
Database
ISI
SICI code
0026-2714(200002)40:2<267:TIOSBS>2.0.ZU;2-N
Abstract
This paper presents the effect of area bumping on device degradation in sca led metal-oxide-semiconductor field-effect transistors (MOSFETs). We have i nvestigated the gate channel length dependence of g(m) degradation after st ud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises's equivalent stress is used to simulate the d istribution of mechanical stress at the gate edges. From the relationship b etween the distribution of the von Mises's equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress con centrates within 0.1 mu m of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices. (C ) 2000 Elsevier Science Ltd. All rights reserved.