Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate

Electric field distribution in the channel of a field effect transistor (FE T) with a field-modulating plate (FP) has been theoretically investigated u sing a two-dimensional ensemble Monte Carlo simulation. This analysis revea led that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric fi eld intensity at the drain side of the gate edge under pinch-off bias condi tions. This study also found that a partial overlap of the high-field regio n under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal-semiconductor FET with FP (F PFET) (L(GF)similar to 0.2 mu m) exhibited a much lower peak electric field intensity than a conventional metal-semiconductor FET. Based on these nume rically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while mai ntaining reasonable gain performance. (C) 2000 American Institute of Physic s. [S0021-8979(00)03506-4].