A TEST METHODOLOGY FOR HIGH-PERFORMANCE MCMS

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, and reliability benefits of MCMs. These advantages are only realized, however, if accompanied by a n efficient test strategy which verifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multi-chip silicon substrate. A test strategy, which addresses testing from the wafer level through to the populated substrate, is detailed. This strategy uses a combinat ion of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Test ing, and Design for Partitionability to ensure high test quality at a reasonable cost. The methodology is then contrasted to alternative app roaches.