Combined asynchronous/synchronous packet switching architecture: QoS guarantees for integrated parallel computing and real-time traffic

Authors
Citation
Y. Ofek et M. Yung, Combined asynchronous/synchronous packet switching architecture: QoS guarantees for integrated parallel computing and real-time traffic, J PAR DISTR, 60(3), 2000, pp. 275-295
Citations number
28
Categorie Soggetti
Computer Science & Engineering
Journal title
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
ISSN journal
07437315 → ACNP
Volume
60
Issue
3
Year of publication
2000
Pages
275 - 295
Database
ISI
SICI code
0743-7315(200003)60:3<275:CAPSAQ>2.0.ZU;2-X
Abstract
This paper focuses on the challenging problem of integrating real-time traf fic with data traffic on the same network, while having predictable quality of service (QoS) guarantees. Predictable QoS guarantees mean both determin istic and probabilistic (with a known probability distribution) functions o f loss, delay, and jitter. As of today there are only limited solutions to this problem. This work presents, to the best of our knowledge, the first c oherent system solution, for combining, on one hand, bursty data traffic wi th deterministic no loss due to congestion, and on the other hand, periodic real-time traffic with deterministic bandwidth guarantees, constant jitter , and bounded delay. The principles of this architecture facilitate the imp lementation of a scalable multimedia system that will combine or integrate distributed/parallel computing (e.g., over a network of PC/workstations) wi th real-time applications (e.g., interactive video teleconferencing). (C) 2 000 Academic Press.