Integrated circuit (IC) feature sizes reaching nanoscale range, it is impor
tant to bridge the gap between modules and chips with design rules similar
to that of IC fabrication technologies, A proper transition calls for impro
ved interconnect design and embedding of IC's to preserve signal integrity.
This paper presents a high performance packaging approach for state-of-the
-art high frequency IC's (HFIC's), Evaporation-, sputtering- and liftoff pr
ocedures were adopted to create smooth, fully planar Au-Cu-Au metallization
on low dielectric constant (k) substrates utilizing a dual-mode transmissi
on line in order to decrease microwave losses in carrier interconnects. A s
pecial attention was put to investigation of via hole formation.