Digital cancellation of D/A converter noise in pipelined A/D converters

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to compo nent mismatches in their internal digital-to-analog converters (DACs). The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise . This paper describes an all-digital technique that significantly mitigate s this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC , so no special calibration signal or auto-calibration phase is required. T he details of the technique are described in the context of a nominal 14-bi t pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the o verall ADC accuracy by several bits with only moderate digital hardware com plexity.