Inherently linear capacitor error-averaging techniques for pipelined A/D conversion

New passive capacitor mismatch error-averaging techniques for pipelined ana log-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital conver ter from reaching a 10-bit and above integral nonlinearity (INL) without tr imming and/or calibration. Simulation results confirm the observation and a case of 14-bit INL realized by 7-bit capacitor matching is shown. The rela xed matching requirement enables the scale-down of the capacitor sizes to t hat of the KT/C limit. As a result, great reductions in both power consumpt ion and chip area can be achieved.