Timing optimization on routed designs with incremental placement and routing characterization

Authors
Changfan, C Hsu, YC Tsai, FS
Citation
C. Changfan et al., Timing optimization on routed designs with incremental placement and routing characterization, IEEE COMP A, 19(2), 2000, pp. 188-196
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN journal
02780070 → ACNP
Volume
19
Issue
2
Year of publication
2000
Pages
188 - 196
Database
ISI
SICI code
0278-0070(200002)19:2<188:TOORDW>2.0.ZU;2-7
Abstract
Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 mu m. Conventional back-an notation approach dots not guarantee timing convergence due to different es timation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental resul ts show that this algorithm provides better result after detail routing is completed.