Simultaneous gate sizing and placement

This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform timing analysis to id entify the set of k most-critical paths in the circuit followed by cell res izing and replacement along the critical path set and their neighboring cel ls. The process is repeated until no further reduction in circuit delay is possible. At the core of this technique lies a mathematical formulation for simultaneous cell sizing and placement subject to timing and position cons traints, We show that the resulting problem formulation is a generalized ge ometric program, which can be solved by solving a sequence of geometric pro grams. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement.