A global wiring paradigm for deep submicron design

Global interconnect is commonly regarded as a key potential bottleneck to t he advancing performance of high-speed integrated circuits. Our previous wo rk has suggested that local interconnect effects can be managed through a d eep submicron design hierarchy that uses 50 000 to 100 000 gate modules as primitive building blocks. The primary goal of this paper is to examine glo bal interconnect effects, within such a design hierarchy, to determine if t here are any significant roadblocks which will prevent National Technology Roadmap for Semiconductors (NTRS) performance expectations from being met. Specifically, the issues of global resistance-capacitance delay, signal tim e-of-flight, inductance. clock and power distribution, and noise are studie d. Results indicate that, while global clock frequencies mill necessarily b e lower than local clock speeds, NTRS expectations should be attainable to the 50-nm technology generation. Achieving these high clock speeds (10-GHz local clock) will be aided by the use of a newly proposed routing hierarchy which limits interconnect effects at each level of a design (local, isochr onous, and global).