Design of real-time image enhancement preprocessor for CMOS image sensor

This paper presents a design of the real-time digital image enhancement pre processor for CMOS image sensor: CMOS image sensor offers various advantage s while it provides lower-quality images than CCD does. In order to compens ate for the physical limitation of CMOS sensor; the spatially adaptive cont rast enhancement algorithm was incorporated into the preprocessor with colo r interpolation, gamma correction, and automatic exposure control. The effi cient hardware architecture for the preprocessor is proposed and was simula ted in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real- time mode, and performed successfully.