Hardware-software co-implementation of a H.263 video codec

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigate d to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion in cludes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of the H.263 video codec i s implemented in software using a RISC processor. This paper also introduce s efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resoluti on block matching algorithm using multiple candidates and spatial correlati on in motion vector fields (MRMCS), is suggested to reduce the chip size. S oftware optimization techniques are also explored by using the statistics o f transformed coefficients and the minimum sum of absolute difference (SAD) obtained fi-om the motion estimator.