Integration of retiming with architectural floorplanning

The concept of improving the timing behavior of a circuit by relocating reg isters is called retiming and was first presented by Leiserson and Saxe. Th ey showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-offs and delay constraints are considered. The main resul t is that the concavity of the trade-off function allows for casting this p roblem into a classical minimum area retiming problem. The solution paves t he way for retiming to be incorporated in the architectural floorplanning s tage of a design flow tailored for deep sub-micron circuits. Some examples and a register-based interconnect strategy suitable to the developed retimi ng technique on global wires is presented. (C) 2000 Elsevier Science B.V. A ll rights reserved.