Low power architectures for digital signal processing

Low power architectures for digital signal processing algorithms requiring inner product computation are presented. In the first step a power efficien t memory organization exploiting data reuse is determined. In the second st ep an order of evaluation of the partial products that reduces the switchin g activity at the inputs of the computational units is derived, Information related to both coefficients which are static and data which are dynamic, is used to drive the reordering of computation. Experimental results for se veral signal processing algorithms prove that the proposed techniques lead to significant savings in net switching activity and thus in power consumpt ion. (C) 2000 Elsevier Science B.V. All rights reserved.