Low cost bumping by stencil printing: process qualification for 200 mu m pitch

Area array packages (flip chip, CSP (Chip scale packages) and EGA) require the formation of bumps for the board assembly. Since the established bumpin g methods need expensive equipment and/or are limited by the throughput, mi nimal pitch and yield, the industry is currently searching for new and lowe r cost bumping approaches. The experimental work of stencil printing to cre ate solder bumps for flip chip devices is described in detail in this artic le. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by st encil printing. The experimental results for this technology will be presen ted, and the limits concerning pitch, stencil design, reproducibility and b ump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demand s for ultrafine pitch hip chip assembly are shown. (C) 2000 Elsevier Scienc e Ltd. All rights reserved.