Low voltage micropower log-domain filters

A design technique for low-voltage, micropower continuous-time filters impl ementing CMOS devices operating in weak inversion is presented. The basic b uilding block is the CMOS log-domain integrator. The effects of the MOS dev ice nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz-100 kHz, and it has a power diss ipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was l aid out using the 0.35-mu m mixed-mode polycide CMOS technology and occupie s a die area of 0.04 mm(2) without the i/o pads.