Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a signif icant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in very larg e scale integration (VLSI), namely, 1) parallel lines on a plane and 2) wir es between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with nume rical solutions of three-dimensional (3-D) Poisson's equation as well as me asurement data. The delay and crosstalk models agree well with SPICE simula tions.