WCET analysis of superscalar processors using simulation with Coloured Petri Nets

Determining a tight WCET of a block of code to be executed on a modern supe rscalar processor architecture is becoming ever more difficult due to the d ynamic behaviour exhibited by current processors, which include dynamic sch eduling features such as speculative and out-of-order execution in the cont ext of multiple execution units with deep pipelines. We describe the use of Coloured Petri Nets (CP-nets) in a simulation based approach to this probl em. A complex model of a generic processor architecture is described, with emphasis on the modelling strategy for obtaining the WCET and an analysis o f the results.