A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order Delta Sigma modulator for audio-band ana log-to-digital conversion implemented in a 3.3-V, 0.5-mu m, single-poly CRO S process using metal-metal capacitors that achieves 98-dB peak signal-to-n oise-and-distortion ratio and 105-dB peak spurious-free dynamic range, The design uses a low-complexity, first-order mismatch-shaping 33-level digital -to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator of fsets, These signal-processing innovations, combined with established circu it techniques, enable state-of-the-art performance in CMOS technology optim ized for digital circuits.