Bandwidth extension in CMOS with optimized on-chip inductors

We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry! by using optimized on chip spiral inductors as shunt-peaking ele ments. The series resistance of the on-chip inductor is incorporated as par t of the load resistance to permit a large inductance to be realized with m inimum area and capacitance, Simple, accurate inductance expressions are us ed in a lumped circuit inductor model to allow the passive and active compo nents in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. T he bandwidth extension technique is applied in the implementation of a 2.12 5-Gbaud preamplifier that employs a common-gate input stage followed by a c ascoded common-source stage. On-chip shunt peaking is introduced at the dom inant pole to improve the overall system performance, including a JOB incre ase in the transimpedance. This implementation achieves a 1.6-k Omega trans impedance and a 0.6-mu A input-referred current noise, while operating with a photodiode capacitance of 0.6 pF. A fully differential topology ensures good substrate and supply noise immunity, The amplifier, implemented in a t riple-metal, single-poly, 14-GHz f(Tmax), 0.5-mu m CMOS process, dissipates 225 mW of which 110 mW is consumed by the 50-Omega output driver stage. Th e optimized on-chip inductors consume only 15% of the total area of 0.6 mm( 2).