Low-power direct digital frequency synthesis for wireless communications

A low-power direct digital frequency synthesizer (DDFS) architecture is pre sented. It uses a smaller lookup table for sine and cosine functions compar ed to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memo ry). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity, 29-Hz frequency resolution, and 9-bit output data for sine functio n generation is being implemented in 0.8-mu m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).