Concentrator circuit with multiple priority levels

Authors
Krishnamoorthy, AV Chiou, LY Rozier, RG Kibar, O
Citation
Av. Krishnamoorthy et al., Concentrator circuit with multiple priority levels, ELECTR LETT, 36(6), 2000, pp. 500-501
Citations number
2
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
6
Year of publication
2000
Pages
500 - 501
Database
ISI
SICI code
0013-5194(20000316)36:6<500:CCWMPL>2.0.ZU;2-E
Abstract
The architecture is presented of a memory-less CMOS packet concentrator tha t carries out dynamic statistical multiplexing of data from N inputs to L o utputs with multiple priority levels. Results are presented from a 16-chann el test chip built using 0.5 mu m CMOS technology.