Automatic router for the pin grid array package

A pin grid array (PGA) package router is described. Given a chip cavity wit h a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete t he planar interconnection of pad-to-pin nets on one or more layers. This ro uter consists of three phases: layer assignment, topological routing and ge ometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substr ate layers. Compared to manual routing, this router has a user-friendly gra phic interface and can be applied practically to industrial strength VLSI p ackaging.