PASE-scan design: A new full-scan structure to reduce test application time

Serial scan approaches lead to a considerable reduction in the test generat ion cost for sequential circuits. However, they do present some drawbacks, such as area overhead, I/O pin overhead and high test application time. A n ew full-scan approach is described, named 'PASE-scan design', capable of su bstantially reducing the test application time. The paper focuses particula rly on the case of single PASE-scan structures. An heuristic procedure is p roposed to establish the configuration of the single PASE-scan structure an d the placing of its memory elements. The experiments carried out with a se t of ISCAS89 circuits show reductions in test length, with respect to the f ull single serial scan-path case, of up to 91% and 87%, depending on the co mpaction (low or normal) of the applied test set, and average reductions of 62% and 55%, respectively.