Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

The multiplier-free design of transforms implemented in LUT-based FPGAs is presented. To fit bit-level grain size in the FPGA device at algorithm leve l the authors use modified distributed arithmetic (DA) and a named adder-ba sed DA to formulate bit-level transform expressions, then they further mini mise hardware cost by the proposed vertical subexpression sharing. For impl ementation, the required input buffer design is also considered by employin g FPGA device characteristics and cyclic formulation. The proposed design c an offer savings in excess of two-thirds of hardware cost compared with ROM -based DA.