Method for alleviating voltage limit violations using combined DC optimisation and AC power flow technique

Authors
Wan, HB Bradley, ME Ekwue, AO Chebbo, AM
Citation
Hb. Wan et al., Method for alleviating voltage limit violations using combined DC optimisation and AC power flow technique, IEE P-GEN T, 147(2), 2000, pp. 99-104
Citations number
16
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEE PROCEEDINGS-GENERATION TRANSMISSION AND DISTRIBUTION
ISSN journal
13502360 → ACNP
Volume
147
Issue
2
Year of publication
2000
Pages
99 - 104
Database
ISI
SICI code
1350-2360(200003)147:2<99:MFAVLV>2.0.ZU;2-O
Abstract
An approach of combining DC linear optimisation and AC power flow calculati ons to alleviate voltage limit violations in power systems is presented. A notable feature of this approach is incorporating voltage constraints in a DC optimisation algorithm. The test results show the effectiveness and effi ciency of the technique when applied to the National Grid Company system.