A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets

We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick, We h ave achieved devices with real N- arsenic implanted extensions and BF2 pock ets. The devices operate reasonably well down to 20-nm physical gate length , These devices are the shortest devices ever reported using a conventional architecture.