Design optimization of high-performance low-temperature 0.18 mu m MOSFET'swith low-impurity-density channels at supply voltage below 1 V

A 0.18 mu m nMOS structure with a vertically nonuniform low-impurity-densit y channel (LIDC) at 77 K has been studied at supply voltage below 1 volt. A n abrupt Gaussian profile is used in the channel, The investigation is base d on two-dimensional (2-D) energy transport simulation with appropriate mod els to account for quantum and low-temperature freeze-out effects, The stud y focuses on achieving high driving capability and low off-current at low s upply voltage and on minimizing short channel effects. Some guidelines are proposed for improving device performance and suppressing short-channel eff ects of the LIDC MOS devices, It is shown that at 77 K the optimized nonuni form LIDC 0.18 mu m nMOS structure with an abrupt impurity channel profile at supply voltage as low as 0.9 V is able to provide a saturation drain cur rent comparable to that of a room-temperature LIDC 0.1 mu m nMOS device at 1.5 V, Furthermore, the 77 K LIDC 0.18 mu m nMOS consumes considerably lowe r dynamic and standby power than the room-temperature 0.1 mu m nMOS, These results suggest that the LIDC MOS structure with an abrupt channel profile is very suitable for low-power and high-speed ULSI applications at low temp erature.