RF potential of a 0.18-mu m CMOS logic device technology

The radio-frequency (rf) performance of a 0.18-mu m CMOS logic technology i s assessed by evaluating the cutoff and maximum oscillation frequencies (f( T) and f(max)), the minimum noise figure (F-min) and associated power gain (G(alpha)), and the 1/f-noise of the devices, Gate-biasing and channel-leng th and gate-finger-length adjustments are identified as means to optimize t he rf performance without any technology process modifications, Changing to N2O gate dielectrics is shown to greatly reduce the 1/f noise without sacr ificing the ac performance. The power amplifier characteristics of CMOS at low power levels are also discussed.