The UniMIN switch architecture for large-scale ATM switches

A general expansion architecture is proposed that can be used in building l arge-scale switches using any type of asynchronous transfer mode (ATM) swit ch, The proposed universal multistage interconnection network (UniMIN) swit ch is composed of a buffered distribution network (DN) and a column of outp ut switch modules (OSM's), which can be any type of ATM switch. ATM cells a re routed to their destination using a two-level routing strategy. The DN p rovides each incoming cell with a self-routing path to the destined OSM, wh ich is the switch module containing the destination output port. Further ro uting to the destined output port is performed by the destination OSM, Use of the channel grouping technique yields excellent delay/throughput perform ance in the DN, and the virtual FIFO concept is used for implementing the o utput buffers of the distribution module without internal speedup. We also propose a "fair virtual FIFO" to provide fairness between input lin ks while preserving cell sequence. The distribution network is composed of one kind of distribution module which has the same size as the OSM, regardl ess of the overall switch size N. This gives good modular scalability in th e UniMIN switch. Performance analysis for uniform traffic and hot-spot traf fic shows that a negligible delay and cell loss ratio in the DN can be achi eved with a small buffer size, and that DN yields robust performance even w ith hot-spot traffic. In addition, a fairness property of the proposed fair virtual FIFO is shown by a simulation study.