Analysis of the metastable behaviour of a BiCMOS SR latch

The successful design of digital systems with asynchronous inputs requires careful management of timing relations. Flip-flops used as arbiters or sync hronizers in these systems are under asynchronous control and thus can suff er from additional propagation delays due to metastable operation. These ad ded delays lead to system malfunction. An analysis of metastable operation in BiCMOS SR flip-flops is presented. An analytical expression for the flip -flop resolving time is derived. Optimal sizing of the MOSFETs and BJTs is investigated analytically as well as by using SPICE simulation.