Overview of status and challenges of system testing on chip with embedded DRAMS

The combination of logic together with DRAM as a system on chip (SOC) has m any advantages for a large variety of computing and network applications. T he goal of testing a system is to detect the fabrication caused faults in o rder to guarantee the defined quality. The increasing size of memories, shr inking dimensions, higher demands on application (frequency and temperature range) and quality cause new problems and higher costs of testing. On the other hand the pressure to serve the market with low cost products forces t he test engineer to reduce test costs by reducing test times and using low cost test equipment. Different solutions are discussed in this paper in ord er to meet these challenges. The variety of test approaches for testing SOC with embedded DRAMs reaches from testing with completely chip external tes t logic, a simple on-chip test logic up to a full blown built-in self test (BIST) on chip. Which choice is the right one depends on different criteria e.g. memory size, quality demands and application of the product. As an ex ample the modular embedded DRAM core concept from Infineon Technologies is discussed, which includes a dedicated modular test concept based on on-chip integration of a test controller. (C) 2000 Published by Elsevier Science L td. All rights reserved.