Optimization of 0.18 mu m CMOS devices by coupled process and device simulation

Coupled process and device simulation is applied for the optimization of th e doping in 0.18 mu m CMOS transistors. An advanced device architecture wit h a pocket type doping around the source/drain extensions was assumed to re duce the short channel effects. Two optimization targets were considered: t he drain drive current at a fixed leakage current and a special figure of m erit which characterizes the maximum switching frequency of the transistors . The method of response surface modeling was used to find the optimum cond itions for the critical implantation steps which form the doping distributi on in the active areas of the transistors. The simulation results show that an increase of the implantation dose of the source and drain extensions to values of 5 x 10(14)-10(15) cm(-2) improves both the drain drive current a nd the maximum switching frequency of the transistors. A three-dimensional simulation of the narrow channel transistors shows a significant non-unifor mity in the lateral current distribution with the current maximum located a t the edges of the active area of such transistors. (C) 2000 Published by E lsevier Science Ltd. All rights reserved.