An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to bu ild a different rule-checking ASIC each time design rules or fabrication re cesses change. In this paper, we propose a configurable hardware approach t o DRC. It can garner impressive speedups over software approaches, while re taining the flexibility needed to change the rule checker as rules or proce sses change. Our work proposes an edge-endpoints-based method for performing Manhattan g eometry checking and a general scalable architecture for DRC. We then demon strate our approach by applying this architecture to a set of design rules for MOSIS SCN4N_SUB process. We have implemented several design rule checks within a single Xilinx XC4013 FPGA and demonstrated overall speedups in ex cess of 25X over software methods. We have used a Compaq Pamette board to d o the hardware prototyping and have achieved a clock rate of 33 MHz.