Design of self-checking fully differential circuits and boards

Citation
M. Lubaszewski et al., Design of self-checking fully differential circuits and boards, IEEE VLSI, 8(2), 2000, pp. 113-128
Citations number
21
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
8
Issue
2
Year of publication
2000
Pages
113 - 128
Database
ISI
SICI code
1063-8210(200004)8:2<113:DOSFDC>2.0.ZU;2-G
Abstract
A design methodology for on-line testing analog Linear fully differential ( FD) circuits is presented in this work. The test strategy is based on concu rrently monitoring via an analog checker the common mode (CM) at the inputs of all amplifiers. The totally self-checking (TSC) goal is achieved for li near FD implementations provided that the checker CM threshold is small eno ugh with respect to the specified margins of erroneous behavior in the circ uit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/s oft-fault model, A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. Th e circuit outputs are accepted to deviate within a 10% band. With the imple mented checker, the TSC goal is not achieved for some faults in narrow regi ons of the frequency band. For the worst case, a hard fault which results i n a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an ac cepted output deviation of 15%, This is, however, more demanding on the che cker (which currently takes less than 3% of the total area and about 7.6% o f the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the c hecker strongly code disjoint (SCD), This is easy to implement since an off -line test is also required for the checker. The checker outputs a double-r ail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. Th e circuit-level mixed-signal approach is extended to the board level by mea ns of the IEEE Std. 1149.1 digital test bus.