High-performance carry chains for FPGA's

Carry chains are an important consideration for most computations, includin g FPGA's. Current FPGA's dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper, we demonstrate ho w more advanced carry constructs can be embedded into FPGA's, providing sig nificantly higher performance carry computations. We redesign the standard ripple carry chain to reduce the number of logic levels in each cell. We al so develop entirely new carry structures based on high-performance adders s uch as carry select, carry lookahead, and Brent-Kung. Overall, these optimi zations achieve a speedup in carry performance of 3.8 times over current ar chitectures.