Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

Citation
Ll. Song et al., Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs, IEEE VLSI, 8(2), 2000, pp. 160-172
Citations number
27
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
8
Issue
2
Year of publication
2000
Pages
160 - 172
Database
ISI
SICI code
1063-8210(200004)8:2<160:HCOFFD>2.0.ZU;2-Z
Abstract
Reed-Solomon (RS) coders are used for error-control coding in many applicat ions such as digital audio, digital TV, software radio, CD players, and wir eless and satellite communications. Traditionally, RS coders have been impl emented using dedicated hardware. This paper considers software-based imple mentation of RS codecs, A hardware-software codesign approach is used to de sign the finite field datapath in a domain-specific digital signal processo r (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polyn omial as well as the field degree m, A novel heterogeneous digit-serial app roach is proposed, where the heterogeneity corresponds to the use of differ ent digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGR ED) subarrays, The salient feature of this digit-serial approach is that on ly the digit cells are implemented in hardware and the finite field multipl ications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for d igit-serial finite field multiplications are presented and applied to the d esign of low-energy high-performance RS codecs in software. Significant ene rgy and energy-latency reductions can be achieved using the digit-serial da tapaths, as compared with the traditional approach where a combined MAC-DEG RED (parallel multiplier) unit is used. It is concluded that for two-error- correcting RS(n, k) codes over finite field GF(2(8)), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and ener gy-latency products; with these datapath architectures and appropriate digi t-serial scheduling strategies, more than 60% energy reduction and more tha n one-third energy-latency reduction can be achieved compared with the para llel multiplication datapath-based approach.