Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit si mulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treate d as a distributed RC line can be over 35% for current on-chip interconnect . It is also shown that the traditional quadratic dependence of the propaga tion delay on the length of the interconnect for RC lines approaches a line ar dependence as inductance effects increase. On-chip inductance is therefo re expected to have a profound effect on traditional high-performance integ rated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting rep eaters into RLC lines that are highly accurate with respect to numerical so lutions, RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance i s considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling, Thus, the importanc e of inductance in high-performance very large scale integration (VLSI) des ign methodologies will increase as technologies scale.