Path delay fault simulation of sequential circuits

A differential algorithm for concurrent simulation of path delay faults in sequential circuits is presented. The simulator analyzes all three conditio ns, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output for vector pairs and cons iders the hazard states occurring between vectors. The main contribution is in methods of propagating signals between time frames. An optimistic metho d assumes that ail nondestination flip-flops are not affected by delays. Th e pessimistic method converts all nondestination flip-flops with nonsteady values to the unknown state before these values are propagated beyond the t ime frame in which a path is activated. A 13-valued algebra is shown to imp rove the efficiency of fault simulation.