Automatic target recognition with dynamic reconfiguration

This paper describes the acceleration of an infrared automatic target recog nition (IR ATR) application with a co-processor board that contains multipl e field programmable gate array (FPGA) chips. Template and pixel level para llelism is exploited in an FPGA design for the bottleneck portion of the ap plication. The implementation of this design achieved a speedup of 21 compa red to running on the host processor. The paper then describes an FPGA reso urce manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can b e reconfigured for other purposes. The IR ATR application was ported to wor k with the RM and has been shown to adapt to the amount of reconfigurable h ardware that is available at the time the application is executed.