A simple processor core design for DCT/IDCT

This paper presents a cost effective processor core design that features th e simplest hardware and is suitable for discrete cosine transform/indiscret e cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two dimensional DCT algorithm , the bit-level adder-based distributed arithmetic, and common subexpressio n sharing;to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easil y scaled for higher throughput rate requirements. The DCT design has been i mplemented by 0.6 mu m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm(2), The proposed design can meet real-time DCT/IDCT requirement s of H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional com puting power for other operations when operating at 33 Mhz.