Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates

Citation
Cs. Yang et al., Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates, J VAC SCI B, 18(2), 2000, pp. 683-689
Citations number
15
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Material Science & Engineering
Journal title
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B
ISSN journal
10711023 → ACNP
Volume
18
Issue
2
Year of publication
2000
Pages
683 - 689
Database
ISI
SICI code
1071-1023(200003/04)18:2<683:SOLAST>2.0.ZU;2-V
Abstract
This article describes the formation of amorphous silicon thin film transis tors (TFTs) on glass and flexible transparent plastic substrates using rf p lasma enhanced chemical vapor deposition and a maximum processing temperatu re of 110 degrees C. Silane diluted with hydrogen was used for the preparat ion of the amorphous silicon, and SiH4/NH3/N-2 or SiH4/NH3/N-2/H-2 mixtures were used for the deposition of the silicon nitride gate dielectric. The a morphous silicon nitride layers were characterized by transmission infrared spectroscopy and current-voltage measurements; the plastic substrates were 10 mil thick (0.25 mm) polyethylene terephthalate sheets. Transistors form ed using the same process on glass and plastic showed linear mobilities ran ging from 0.1 to 0.5 cm(2)/V s with I-ON/I-OFF ratios greater than or equal to 10(7). To characterize the stability of the transistors on glass, n- an d p-channel transconductances were measured before and after bias stressing . Devices formed at 110 degrees C show evidence of charge trapping near the a-Si/SiNx interface and the creation of dangling-bond defects. The defect dynamics are consistent with the defect pool model. Under +10 and +25 V bia s stress, the rates of creation of low energy defects are only moderately l arger than those for high temperature devices; the devices show markedly hi gher rates of defect creation under higher positive bias. Current-voltage a nalysis of low temperature dielectrics shows very low leakage, but positive bias stress shows a significantly higher electron trapping rate near the a -Si:H/SiNx interface, indicating problems with low temperature dielectric f ormation. The magnitude of the rates of defect creation and trapping in the se nonoptimized devices suggests that amorphous silicon TFTs with stability approaching that of typical large area active matrix electronic devices co uld be formed at low temperatures compatible with transparent flexible poly meric substrates. (X) 2000 American Vacuum Society. [S0734-211X(00)05402-0] .